1. Field of the Invention
The present invention pertains to the field of high-density memories and, particularly, memories that utilize ferroelectric capacitors.
2. Statement of the Problem
Ferroelectric memories are nonvolatile memories offering performance and densification advantages over conventional nonvolatile memories, such as electrically erasable programmable read only memories (EEPROM) and erasable programmable read only memories (EPROM). U.S. Pat. No. 5,046,043 issued Sep. 3, 1991 to Miller et al. shows a 1T/1C memory cell having a lead zirconium titanate (PZT) ferroelectric capacitor alternatively stacked over a contact hole or within a conduit leading to the transistor source/drain region. The configuration of the Miller et al. ferroelectric memory cells is similar to that of a conventional dynamic random access memory (DRAM) cell. However, the operation and timing are different, particularly in that the cell does not need to be refreshed as often because memory storage is relatively permanent. A refresh operation is one in which the memory logic senses the state of the memory cells and writes the state of the memory that has been sensed back to the memory cells in an identical format to that which has been sensed.
Permanence or nonvolatility of memory storage results from the ability of ferroelectric materials to polarize in the presence of an applied electric field, and to retain that polarization state once the field is removed. Thus, a logical one or zero is represented by the polarization state of the ferroelectric material in the capacitor. Memory sense amplifiers and logic circuits are used to determine the polarization state for memory operations in a conventional manner for ferroelectric memories.
U.S. Pat. No. 5,227,855 issued Jul. 13, 1993 to Hisayo S. Momose shows a one-transistor one-capacitor (1T/1C) memory cell where a PZT ferroelectric capacitor resides in a contact hole contacting a source/drain region of the field effect transistor. The purpose of placing the capacitor in the contact hole is to make the memory cell flatter and facilitate the formation of metal wiring layers in the contact holes. A discussion of the prior art in the Momose patent shows the ferroelectric capacitor located above the transistor gate with a wiring layer extending to the side of the gate region for contact with the transistor source/drain region. The thin films in all of these ferroelectric capacitors have a horizontal orientation parallel to that of the underlying substrate. The discussion below shows that designs to place ferroelectric capacitors in transistor contact holes is, to a certain extent, wishful thinking because the contact holes must be exceptionally large.
In high-density memories, a significant problem with placing the ferroelectric capacitor in the contact hole leading to the transistor source-drain region is that the ferroelectric capacitor must be contained within limited surface area due to the small overall size of the device. Ferroelectric polarization depends primarily on crystal grain surface area, which is typically measured in units of microcoulombs per square centimeter. These grains are sometimes referred to as ferroelectric domains. While increasing the thickness of the ferroelectric layer can increase polarization by increasing the number of vertically stacked domains, increasing the thickness also reduces the applied electric field at some of the domains. As a result, the applied field is greater for some domains and less for other domains. A reduced field is less effective at switching domains, and the unequal switching ability in thicker films results in some domains being incompletely switched.
Ferroelectric films, if left in a polarized state, tend to retain their polarization state for periods of weeks, months, or years; however, in actual use, ferroelectric films retain their polarization states for much shorter times because they are sensitive to disturb voltage pulses. Disturb voltage pulses are unidirectional voltage pulses that switch the polarization state in only a portion of the ferroelectric domains. Current ferroelectric memory architecture requires ferroelectric materials to be exposed to disturb voltage pulses. Disturb voltage pulses have been shown to degrade remnant polarization in PZT capacitors having a 1.84×10−4 cm2 surface area to fifty percent of original levels after 107 cycles of 1.0V pulses 1 μs apart with 100 ns rise and fall times. See Moore et al., “The Effect of Small Voltage Pulses on Retained Polarization in Ferroelectric Capacitors” (undated). Thus, the combined effects of low polarization due to small capacitance area together with disturb voltage pulsing requires ferroelectric memories to be refreshed. Even if the disturb pulses do not switch the ferroelectric, sense operations are increasingly prone to errors because the retained polarization has a lower magnitude that is more difficult to read without switching the polarization state of the ferroelectric material.
One way to avoid the problems that are caused by small capacitance area is to provide a capacitor having a large surface area. PCT Publication No. WO 93/12542 published Jun. 24, 1993 to Araujo et al. shows a 1T/1C memory cell having a horizontally oriented, vertically stacked ferroelectric capacitor with a much greater surface area than the transistor component of the memory cell. The ferroelectric capacitor covers a surface area off to the side of the transistor, and only partially overlaps the transistor. The overall surface area of the capacitor is much greater than the contact hole leading to the transistor active area. This semi-overlapping design uses a layered superlattice material as the ferroelectric. The need for ferroelectric capacitors having relatively large surface areas in high-density memories is apparent from the WO 93/12542 memory cell because the ferroelectric capacitor occupies several times the surface area of the transistor device even though layered superlattice materials have better polarizabilities than do comparable PZT films. A further reason for placement of the ferroelectric capacitor off to the side of the transistor is that the metals in the ferroelectric material might otherwise be more prone to diffuse into the transistor active area where they interfere with the intended n and p dopants.
FIG. 1 shows a cross-sectional view of another typical conventional nonvolatile ferroelectric memory 100 of the prior art. Ferroelectric memory capacitor 128 includes bottom electrode 122, ferroelectric thin film 124, and top electrode 126, which are substantially parallel to underlying semiconductor substrate 102. The effective capacitance area of memory capacitor 128 is generally determined by the smallest horizontal surface area of the active capacitor elements. In capacitor 128, active capacitor elements bottom electrode 122, ferroelectric thin film 124, and top electrode 126 have substantially the same horizontal surface area. To increase the polarizability of capacitor 128 of the prior art, it would be necessary to increase the horizontal surface area of the active capacitor elements. This would increase the horizontal surface area (“footprint”) of capacitor 128, thereby decreasing the density of memory 100.
The ever-increasing density of integrated circuits, however, requires a corresponding decrease in the horizontal surface area of memory cells, while maintaining good electronic properties, such as good polarizability and low coercive voltage. Thus, there remains a need to provide a ferroelectric capacitor for high-density memories where the footprint of the capacitor is reduced with a corresponding increase in memory density.